Programmable logic has increasingly become a valued resource for system designers. Programmable logic can allow for a custom logic design to be implemented without the initial cost, delay and complexity of designing and fabricating an application specific integrated circuit (ASIC).
Currently, there are many variations of programmable logic, including simple programmable logic devices (SPLDs), complex PLDs (CPLDs), and field programmable gate arrays (FPGAs) (referred to herein collectively as programmable logic devices (PLDs)).
While PLDs can have numerous applications, one application of increasing value is serial data communications. Increasingly, various electronic devices can communicate with one another with serial data streams of various protocols. A number of factors can effect the efficiency of serial communications. In particular, for many transmission media, it can be desirable to balance bit data values (i.e., the number of consecutive “1” or “0” values). Such balancing is also referred to as generating encoded values having a low (or zero) DC component. Balanced data values can limit baseband wander in a data carrying signal. Along these same lines, it can also be desirable to include a minimum density in the number of transitions in a data value. Transition density can aid in recovering a clock signal for a serial data stream.
One of the many approaches to balancing bit data values includes encoding data words of one bit length into longer bit length data words. Such longer data words may, in some cases, have the same number of zeros and ones. Alternatively, in cases of value mapping, an input data word may be encoded into an output data word having the same bit size.
Among the various well-known encoding schemes are 4/5 bit encoding and 8/10 bit encoding. Such encoding operations will be referred to herein generally as x/y encoding/decoding, where it is understood that x and y are numbers of bits, with x being the number of bits before an encoding operation (or after a decoding operation) and y being the number of bits after an encoding operation (or before a decoding operation). While in many applications x<y, in other operations x=y and/or x>y.
An encoding operation may encode data words of x bits into data words of y bits for various reasons, including those described above. A decoding operation may receive encoded data words of y bits and generate original data words of x bits.
Another type of encoding that may be useful for clock recovery functions is “scrambling.” Scrambling can essentially detect when a sequence of consecutive bits has the same value, and can periodically insert an additional value that may ensure a transition in state occurs within a predetermined time frame. In many cases, a scrambling circuit may include, or be functionally equivalent to, a serial arrangement of shift registers with one or more feedback stages. Such functions may be expressed as a polynomial. Polynomial representation of scrambling functions and circuits are well-known in the art. Further, as in the case of x/y encoding and decoding, scrambling functions may have corresponding de-scrambling functions for extracting the added states.
As noted above, serial data communications can be an important application for an integrated circuit. While fully custom application specific integrated circuits (ASICs) can be developed to meet a particular application, such approaches may be expensive and inflexible. Such approaches can incur expenses, as manufacturing components (e.g., masks, packaging etc.) may have to be custom developed for the ASIC. Such approaches may be inflexible, as changes in a design can be difficult to accommodate without altering existing manufacturing components.
As an alternative to an ASIC, conventional programmable logic solutions have programmed programmable logic devices with serial data communication functions. A typical programmable logic approach can include expressing a desired function in a higher-level design language. Such a function may then be synthesized into actual programmable logic gate configuration/interconnections.
A drawback to such conventional approaches can be the gate “cost” of realizing such serial communication functions on a PLD. As but one example, a conventional 8/10 bit encoder/decoder has been known to require 11,500 gates on a FPGA. Dedicating such a number of gates to one function of a serial communication application reduces the ability of a programmable logic device to accommodate any other functions.
Another drawback to conventional PLD approaches can be flexibility. The particular type of x/y encoding utilized in a system may differ according to particular communication standards. That is, one serial communication standard may have one type of 8/10 bit encoding/decoding, while a second may have a different type of x/y encoding/decoding, while a third may have one type of 4/5 bit encoding/decoding. Likewise, a particular polynomial for scrambling/de-scrambling can likewise vary between standards. Consequently, while one PLD configuration can be synthesized to meet one standard, re-design and re-synthesis may have to be performed to meet a different standard using a different type of encoding/scrambling.
Yet another drawback to conventional programmable logic approaches to serial communication applications can be timing requirements for such applications. For example, in some applications, serial communication operations may have to function in synchronism with a 125 MHz system clock, have input set-up times of about 1.5 nS, latch hold times of about 1.0 nS, and clock to output times of about 5.5 nS. Such timing constraints can be difficult to meet, as a synthesized solution may include signal propagation paths that include gates that are not necessary of a given function, but result from the logic gate layout of a PLD.
In light of the above discussion, it would be desirable to arrive at some way of providing an integrated circuit for serial communication applications that can be more flexible than conventional ASIC and PLD approaches.
It would also be desirable to arrive at some way of providing a programmable device that can provide serial data communication functions without necessarily consuming as many programmable resources as conventional PLD approaches.